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Core
GPU Architecture and Execution
A GPU is not a fast CPU. It runs thousands of threads in lockstep groups called warps across many streaming multiprocessors, under the SIMT model, and its real constraint is moving data through a memory hierarchy that spans fast on-chip registers and shared memory down to slow off-chip HBM. Understanding occupancy, coalesced memory access, and warp divergence is what separates a kernel that hits peak throughput from one that leaves 90% of the chip idle.
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ML Infrastructure & GPUsExplain how the CUDA execution model maps to hardware, grids, blocks, warps, SMs.→ML Infrastructure & GPUsWalk me through the GPU memory hierarchy, registers, shared memory, L2, HBM. What lives where and why?→ML Infrastructure & GPUsWhat is warp divergence and why does it hurt performance?→ML Infrastructure & GPUsExplain memory coalescing and shared-memory bank conflicts. How would you fix a kernel that has both?→ML Infrastructure & GPUsWhat is occupancy, and how do you balance it against register and shared-memory usage when choosing block size?→ML Infrastructure & GPUsHow do you determine whether a kernel is memory-bound or compute-bound?→