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RecentarXiv preprint

FlashAttention-4: Algorithm and Kernel Pipelining Co-Design for Asymmetric Hardware Scaling

Blackwell doubled tensor-core speed but not the exponential unit or shared memory, so softmax and data movement now limit attention. FlashAttention-4 rebalances: 1,613 TFLOPS on B200, 1.3x cuDNN.

Breakdown by FDE Interviews · 12 min read · Updated

About the original · 2026
AUTHORS
Zadouri, Hoehnerbach, Shah, Liu, Thakkar, Dao
FROM
Princeton University, Meta, Colfax Research, NVIDIA, Georgia Tech, Together AI
PUBLISHED
Mar 2026 · arXiv preprint
CITED BY
82Semantic Scholar · Oct 2026
IN THIS BREAKDOWN · 10 SECTIONS

You can read 21% of this breakdown.

01

The paper in one minute

FlashAttention made attention fast by never writing the full attention matrix to GPU memory: it tiles queries and keys, computes softmax on the fly ("online softmax") and keeps everything on chip. Each new GPU generation needs the kernel rebuilt around its hardware: FlashAttention-2 for Ampere, FlashAttention-3 for Hopper.

Blackwell (B200, GB200) changed the balance. Per SM per clock, BF16 tensor-core throughput doubled to 8,192 operations, but the exponential unit stayed at 16 operations and shared memory at 128 bytes. The paper's roofline for a 128×128 tile shows the result: in the forward pass, exponentials (1,024 cycles) now take as long as the matrix multiplies (1,024); in the backward pass, shared-memory traffic (3,328 cycles) exceeds them (2,560) by 30%. Making the matrix math faster no longer helps unless the rest keeps up.

FlashAttention-4 attacks the non-matmul work:

  • Pipeline for asynchronous tensor cores. Blackwell's tensor cores write results to a new 256 KB tensor memory per SM without blocking registers. FA4 processes two query tiles in a ping-pong so one tile's softmax runs while the other's matrix multiplies, and moves output rescaling to a separate warpgroup.
  • Software exponentials. For 10% to 25% of softmax entries, 2^x is computed on the general FMA units: split x into integer and fraction, evaluate a cubic polynomial on the fraction and add the integer to the float's exponent bits. After rounding to BF16, it matches the hardware unit within one unit in the last place on 99% of inputs.
  • Lazy rescaling. Online softmax rescales the running output whenever a new maximum appears. FA4 rescales only when the maximum grows by more than 8 in log2 units (a factor of 256), and fixes up at the end. The result stays exact.
  • Paired-CTA backward pass. Blackwell can run one matrix multiply across two thread blocks, each holding half an operand. That cuts shared-memory traffic for operands and halves the global atomic adds for dQ.

It also orders work tiles longest first for causal masks and variable lengths, offers a deterministic backward mode, and is written in CuTe-DSL in Python. On B200 with BF16, forward attention reached up to 1,613 TFLOPS (71% of peak), 1.1-1.3x cuDNN 9.13 and 2.1-2.7x Triton.

THE IDEA, VISUALLY
ASYMMETRIC SCALING, PER SM PER CLOCK (SECTION 2.2) H100 B200 BF16 tensor cores (ops) 4,096 8,192 2x exponential unit (ops) 16 16 same shared memory (bytes) 128 128 same ROOFLINE, CYCLES PER 128x128 TILE (TABLES 1, 3) forward MMA 1,024 exp 1,024 smem 768 backward MMA 2,560 exp 1,024 smem 3,328 backward, 2-CTA MMA 2,560 exp 1,024 smem 2,688 WHAT FA4 CHANGES (SECTION 3) async MMA into tensor memory; softmax overlaps the next tile 2^x emulated on FMA units for 10-25% of softmax entries rescale running max only when it jumps by > 2^8 backward: 2-CTA MMA halves operand traffic and dQ atomics longest-first tile order for causal and variable-length B200, BF16 (SECTION 4) peak forward throughput 1,613 TFLOPS (71%) vs cuDNN 9.13 1.1-1.3x vs Triton 2.1-2.7x deterministic backward up to 75% of non-det. LPT tile order, MHA / MQA-8 +4-8% / +7-14% seq 1k-32k, 32k tokens per batch, head dim 64, 128, (192,128) COMPILE TIME PER KERNEL (TABLE 4) forward FA3 C++ 55 s FA4 Python DSL 2.5 s backward FA3 C++ 45 s FA4 Python DSL 1.4 s EMULATED 2^x ACCURACY (TABLE 2) float32 max relative error: degree 3 8.8e-5, hardware 1.4e-7; after rounding to BF16 both ~3.9e-3 degree 3 within 1 BF16 ULP of hardware on 99% of inputs code: Dao-AILab/flash-attention (flash_attn/cute)
On Blackwell, matrix math got twice as fast per clock but exponentials and shared memory did not, so FlashAttention-4 spends its effort hiding and shrinking the non-matmul work.
Research notes: the problem, approach and results
1,613

TFLOPS for BF16 forward attention on one B200, 71% of the 2.25 PFLOPS peak

1.1-1.3x

faster than cuDNN 9.13's attention on B200 (2.1-2.7x faster than Triton)

22-32x

faster kernel compilation than FlashAttention-3 (55 s to 2.5 s forward, 45 s to 1.4 s backward)

THE PROBLEM

FlashAttention-3 was built for Hopper. Blackwell GPUs (B200, GB200) double tensor-core throughput per SM while the exponential unit and shared-memory bandwidth stay the same, so in attention the softmax exponentials and shared-memory traffic now take as long as, or longer than, the matrix multiplies. Hopper's instructions also don't carry over.

THE IDEA

Redesign the pipeline around Blackwell's fully asynchronous tensor cores and tensor memory so softmax overlaps matrix math; compute part of the exponentials in software on the FMA units with a cubic polynomial; skip rescaling the running output unless the max jumps by more than 2^8; and in the backward pass use paired-CTA matrix operations to cut shared-memory traffic and halve dQ atomic adds. Write it all in a Python DSL.

THE RESULT

On B200 with BF16, forward attention reached up to 1,613 TFLOPS (71% of peak), 1.1-1.3x cuDNN 9.13 and 2.1-2.7x Triton, with backward speedups as well. Kernels compile in 1.4-2.5 seconds against 45-55 for FlashAttention-3's C++ templates.

02

Why it matters to an FDE

Customers buying Blackwell expect their models to get faster. For long-context inference and training, attention is often the largest single cost, and its speed depends on whether the software stack has kernels written for the new hardware.

Check the attention kernel version, not just the GPU. Running Hopper-era kernels (or generic fallbacks) on Blackwell leaves much of the hardware idle. Serving and training frameworks pick up FA4-class kernels on their own schedules; confirm what a deployment actually runs.

Long sequences gain most. The paper's speedups are largest from 4K tokens up and with causal masks, the regime of long-document, codebase and reasoning workloads.

Faster hardware shifts bottlenecks rather than removing them. The paper's roofline argument (matrix units doubling while exponentials and memory stay flat) applies to any kernel. When a new GPU underdelivers on a workload, look at the non-matmul work.

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  • ◇1 architecture diagram
  • </>1 runnable code experiment
  • ▦2 results tables
  • ?5 interview questions with answers
  1. 03Key takeaways

    The roofline, the four techniques, scheduling, determinism, the DSL and three misreadings

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  2. 04How it works

    The forward pipeline, the exponential emulation, lazy rescaling, the backward pass and scheduling

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  3. 05The numbers that matter

    Roofline tables, exponential accuracy, benchmark setup and results, compile time

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  4. 06Try it yourself

    Rebuild the roofline, emulate 2^x, test lazy rescaling and schedule causal tiles

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  5. 07Where it breaks

    Blackwell-only design, tuning knobs, evaluation scope and slips

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  6. 08Using it on a deployment

    Confirming the kernel path on Blackwell, where gains show up, and what to benchmark

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  7. 09Interview angles

    Five questions this paper prepares you for, with answer hints

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