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The paper in one minute
Training mostly runs dense attention on fixed-size batches. Serving doesn't. The KV cache lives in pages (vLLM) or a radix tree (SGLang); a batch mixes new prompts and single-token decodes; many requests share a system prompt; speculative decoding verifies trees of guesses; and models keep adding attention variants (sliding windows, logit soft-capping, fused rotary embeddings). Each engine had been writing its own kernels for its own subset.
FlashInfer is an attention library built for that mix, with three ideas.
One format for every KV layout. A page table or a prefix tree is a block-sparse row (BSR) matrix: rows are queries, columns are KV blocks, and a non-zero block means "this query attends to this page". FlashInfer's kernels accept any block size, gathering scattered pages into contiguous shared memory before using tensor cores. Composable formats split one cache into two views: a shared prefix stored with a large row block (many queries together), so its KV is loaded once into fast on-chip memory for the whole group; and each request's own tokens with single-row blocks. No data moves; only the index arrays differ.
Customizable attention, compiled just in time. A variant is specified as small functions (query and key transforms such as RoPE, a logits transform such as soft-capping, a mask), and FlashInfer generates CUDA from FlashAttention-2 or -3 templates, picking a query tile size (1 to 128) to match the batch's average query length.
Load balancing that survives CUDA graphs. Each step, a CPU-side plan splits long KV sequences into equal chunks across the GPU's processors and records where partial results go; persistent kernels with fixed grid sizes then run inside a captured graph and merge partial results with the log-sum-exp composition.
Integrated into SGLang, vLLM and MLC-Engine, it cut SGLang's median inter-token latency 29-69% against Triton kernels, StreamingLLM latency 28-30% with a fused kernel, and parallel-generation inter-token latency 13.7-17.4% with composable formats.
Research notes: the problem, approach and results
lower median inter-token latency in SGLang with FlashInfer than with its Triton attention backend
more memory bandwidth used by a fused RoPE-plus-attention kernel than separate RoPE and attention kernels
major serving engines integrating it: SGLang, vLLM and MLC-Engine
Serving engines need attention kernels for many shapes at once: paged or tree-structured KV caches, prefill and decode mixed in one batch, shared prefixes, speculative trees, and new attention variants. Batches have very uneven lengths that leave GPU cores idle, and CUDA graphs, which serving relies on to cut launch overhead, require fixed launch configurations.
Represent any KV layout as a block-sparse row matrix (queries by KV blocks) with arbitrary block sizes, and combine formats so shared prefixes use bigger blocks read once into shared memory. Provide an attention template whose variants (masks, logit transforms, RoPE) are compiled just in time. Plan work on the CPU each step to split long KV evenly across processors with persistent kernels that stay CUDA-graph compatible.
Inside SGLang, median inter-token latency fell 29-69% against the Triton backend on Llama 3.1 8B and 70B. A fused RoPE kernel cut StreamingLLM latency 28-30%, and composable formats cut inter-token latency 13.7-17.4% for parallel generation.
Why it matters to an FDE
Most engineers never call FlashInfer directly; it sits under the serving engine. It still shows up in deployments in three ways.
It's a setting. SGLang and vLLM let you choose the attention backend. On the same model and GPU, the choice changed inter-token latency by up to 69% in the paper's SGLang tests, so check which backend a slow deployment uses before tuning anything else.
New model features need kernel support. A model with soft-capped logits, an unusual mask or a new positional scheme runs slowly, or not at all, until the attention kernels support it. JIT templates are what let engines support new variants quickly.
Batch shape matters. Mixed lengths, shared prompts and parallel sampling all change which kernel path is fastest. If a customer's traffic is highly skewed (a few very long contexts among many short ones), load-balanced kernels are what keep the GPU busy.
Understand the mechanism. Try it on a real problem.
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- ◇1 architecture diagram
- </>1 runnable code experiment
- ▦2 results tables
- ?5 interview questions with answers
- 03Key takeaways
Block-sparse KV, composable formats, tile selection, plan/run scheduling and three misreadings
Free account - 04How it works
The BSR format, data loading, JIT variants, the planner and the API
Premium - 05The numbers that matter
Serving results, kernel utilization, long-context and parallel generation
Premium - 06Try it yourself
Run attention through a BSR page table, count prefix reads, balance skewed batches and size tiles
Premium - 07Where it breaks
NVIDIA-only kernels, CPU planning cost, benchmark scope and slips
Premium - 08Using it on a deployment
Choosing the attention backend, checking variant support, and testing on real batch shapes
Premium - 09Interview angles
Five questions this paper prepares you for, with answer hints
Premium - 10Read next
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